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101 Innovation Drive San Jose, CA 95134 www.altera.com DSP Builder Installation and Licensing Software Version: 9.0 Document Date: March 2009.

System Generator for DSP™ is the industry’s leading high-level tool for designing high-performance DSP systems using Xilinx All Programmable devices. With System Generator for DSP, create production-quality DSP algorithms in a fraction of time compared to traditional RTL. Develop highly parallel systems with the industry’s most advanced FPGAs. Provide system modeling and automatic code generation from Simulink® and MATLAB® (The Mathworks, Inc.). Integrates RTL, embedded, IP, MATLAB and hardware components of a DSP system. A key component of the Xilinx DSP Targeted Design Platform System Generator for DSP is part of the Vivado® System Edition Design Suite. With System Generator for DSP, developers with little FPGA design experience can quickly create production quality FPGA implementations of DSP algorithms in a fraction of traditional RTL development times.

Dsp Builders Denver

Support for MATLAB 2015B includes tighter integration allowing HDL Coder to automate the generation of a combined model containing high level RTL and target optimized IP. Simplified IPs enable up-conversion, down-conversion, and standard digital signal processing designs to deliver high quality of results and performance while minimizing the interfaces and number of parameters required to configure the IP. New IPs include Digital FIR Filter, Sine Wave generator, Product, and Requantize block. JTAG co-simulation support for Virtex-7, Kintex-7, Artix-7, and Zynq-7000 families are enhanced and can utilize burst mode to improve performance by up to 45x. Improved launch times and better cross-probing support for the Waveform Viewer and Timing Analyzer aid in the debugging of logic and visualizing timing critical paths.

Vivado integration Part of the Xilinx DSP Targeted Design Platform linked with the Vivado® integrated design environment, IP catalog and High-Level Synthesis. Quickly import Vivado High-Level Synthesis IP for modeling with Simulink®. Automatically generate IP and export to the Vivado IP Catalog. Seamlessly incorporate your DSP algorithm into Xilinx All Programmable SoCs or FPGAs.

DSP modeling Build and debug high-performance DSP systems in Simulink using the Xilinx Blockset that contains functions for signal processing (e.g., FIR filters, FFTs), error correction (e.g., Viterbi decoder, Reed-Solomon encoder/decoder), arithmetic, memories (e.g., FIFO, RAM, ROM), and digital logic. Bit and cycle accurate floating and fixed-point implementation System Generator supports bit and cycle accurate fixed-point and bit and cycle accurate single, double and custom precision floating-point. Automatic code generation of VHDL or Verilog from Simulink Implement behavioral (RTL) generation and target specific Xilinx IP cores from the Xilinx Blockset. Generate IP for quick importation into the Vivado IP Catalog for easy design reuse and model sharing. Hardware co-simulation A code generation option that allows you to validate working hardware and accelerate simulations in Simulink and MATLAB. System Generator supports Ethernet (10/100/Gigabit) and JTAG communication between a hardware platform and Simulink.: Kintex®-7, Virtex®-7, Zynq®-7000, Artix®-7, Kintex UltraScale™, Virtex UltraScale.

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